/*
 * Copyright (C) 2015 Spreadtrum Communications Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *************************************************
 * Automatically generated C header: do not edit *
 *************************************************
 */

/*
 * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit,
 * Voltage Trimming (4)Ctrl and (5)Bits, Calibration (6)Ctrl and (7)Bits,
 * Voltage (8)Default, Voltage (9)Ctrl and (10)Bits, Voltage Select (11)Count and Voltage (12)List[ ... ...]
 */
    SCI_REGU_REG(vddcore, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_CORE_PD,
	ANA_REG_GLB_DCDC_CORE_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8), ANA_REG_GLB_DCDC_CH_CTRL, BIT(13)|BIT(14)|BIT(16)|BIT(18)|BIT(19),
	900, 0, 0, 2, 0, 3125);
    SCI_REGU_REG(vddgen, 0x12, ANA_REG_GLB_POWER_PD_SW, BIT_DCDC_GEN_PD,
	ANA_REG_GLB_DCDC_GEN_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_DCDC_CH_CTRL, BIT(13)|BIT(14)|BIT(16)|BIT(18)|BIT(19),
	1850, 0, 0, 2, 1300, 12500);
    SCI_REGU_REG(vddwpa, 0x2, ANA_REG_GLB_DCDC_WPA_REG2, BIT_PD_BUCK_VPA,
	ANA_REG_GLB_DCDC_WPA_VOL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), 0, BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19),
	0, 0, 0, 0);
    SCI_REGU_REG(avdd18, 0x10, ANA_REG_GLB_POWER_PD_SW, BIT_LDO_AVDD18_PD,
	ANA_REG_GLB_LDO_AVDD18_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1800, 0, 0, 2, 1400, 12500);
    SCI_REGU_REG(vddcamio, 0x0, ANA_REG_GLB_LDO_CAMIO_REG0, BIT_LDO_CAMIO_PD,
	ANA_REG_GLB_LDO_CAMIO_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1800, 0, 0, 2, 1400, 12500);
    SCI_REGU_REG(vddrf18a, 0x10, ANA_REG_GLB_LDO_RF18A_REG0, BIT_LDO_RF18A_PD,
	ANA_REG_GLB_LDO_RF18A_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1800, 0, 0, 2, 1400, 12500);
    SCI_REGU_REG(vddrf18b, 0x00, ANA_REG_GLB_LDO_RF18B_REG0, BIT_LDO_RF18B_PD,
	ANA_REG_GLB_LDO_RF18B_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1800, 0, 0, 2, 1400, 12500);
    SCI_REGU_REG(vddcamd, 0x0, ANA_REG_GLB_LDO_CAMD_REG0, BIT_LDO_CAMD_PD,
	ANA_REG_GLB_LDO_CAMD_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1200, 0, 0, 2, 800, 12500);
    SCI_REGU_REG(vddcon, 0x0, ANA_REG_GLB_LDO_CON_REG0, BIT_LDO_CON_PD,
	ANA_REG_GLB_LDO_CON_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1200, 0, 0, 2, 800, 12500);
    SCI_REGU_REG(ldomem, 0x10, ANA_REG_GLB_POWER_PD_SW, BIT_LDO_MEM_PD,
	ANA_REG_GLB_LDO_MEM_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1200, 0, 0, 2, 800, 12500);
    SCI_REGU_REG(vddsim0, 0x0, ANA_REG_GLB_LDO_SIM0_PD_REG, BIT_LDO_SIM0_PD,
	ANA_REG_GLB_LDO_SIM0_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3000, 0, 0, 2, 1612, 12500);
    SCI_REGU_REG(vddsim1, 0x0, ANA_REG_GLB_LDO_SIM1_PD_REG, BIT_LDO_SIM1_PD,
	ANA_REG_GLB_LDO_SIM1_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3000, 0, 0, 2, 1612, 12500);
    SCI_REGU_REG(vddsim2, 0x0, ANA_REG_GLB_LDO_SIM2_PD_REG, BIT_LDO_SIM2_PD,
	ANA_REG_GLB_LDO_SIM2_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3000, 0, 0, 2, 1612, 12500);
    SCI_REGU_REG(vddcama, 0x0, ANA_REG_GLB_LDO_CAMA_REG0, BIT_LDO_CAMA_PD,
	ANA_REG_GLB_LDO_CAMA_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(9)|BIT(17)|BIT(18)|BIT(20),
	2800, 0, 0, 2, 1612, 12500);
    SCI_REGU_REG(vddcammot, 0x0, ANA_REG_GLB_LDO_CAMMOT_REG0, BIT_LDO_CAMMOT_PD,
	ANA_REG_GLB_LDO_CAMMOT_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(9)|BIT(17)|BIT(18)|BIT(20),
	3000, 0, 0, 2, 2000, 12500);
    SCI_REGU_REG(vddemmccore, 0x10, ANA_REG_GLB_LDO_EMMCCORE_PD_REG, BIT_LDO_EMMCCORE_PD,
	ANA_REG_GLB_LDO_EMMCCORE_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3000, 0, 0, 2, 2000, 12500);
    SCI_REGU_REG(vddsdcore, 0x10, ANA_REG_GLB_LDO_SD_PD_REG, BIT_LDO_SDCORE_PD,
	ANA_REG_GLB_LDO_SD_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3000, 0, 0, 2, 2000, 12500);
    SCI_REGU_REG(vddsdio, 0x10, ANA_REG_GLB_LDO_SDIO_PD_REG, BIT_LDO_SDIO_PD,
	ANA_REG_GLB_LDO_SDIO_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3000, 0, 0, 2, 1612, 12500);
    SCI_REGU_REG(vdd28, 0x10, ANA_REG_GLB_POWER_PD_SW, BIT_LDO_VDD28_PD,
	ANA_REG_GLB_LDO_VDD28_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	2800, 0, 0, 2, 1612, 12500);
    SCI_REGU_REG(vddwifipa, 0x0, ANA_REG_GLB_LDO_WIFIPA_REG0, BIT_LDO_WIFIPA_PD,
	ANA_REG_GLB_LDO_WIFIPA_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3300, 0, 0, 2, 2100, 12500);
    SCI_REGU_REG(vdddcxo, 0x10, ANA_REG_GLB_POWER_PD_SW, BIT_LDO_DCXO_PD,
	ANA_REG_GLB_LDO_DCXO_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	1800, 0, 0, 2, 1500, 12500);
    SCI_REGU_REG(vddusb33, 0x10, ANA_REG_GLB_LDO_USB_PD_REG, BIT_LDO_USB33_PD,
	ANA_REG_GLB_LDO_USB_REG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_DCDC_CH_CTRL, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20),
	3300, 0, 0, 2, 2100, 12500);
